IBM tips 32nm with high-k gate-first design

Business and Law

By Rick C. Hodgin

Armonk (NY) - IBM announced a new follow-on step to their January 29, 2007 announcement, that of a high-k/metal gate semiconductor process technology. Scheduled to be "available to IBM alliance members" in the second half of 2009, the new process has demonstrated working silicon at the 32nm process node, including SOI. IBM's partners in the project include AMD, Chartered, Freescale, Infineon, and Samsung. IBM's laboratory tests in East Fishkill, NY, have confirmed a 45% reduction in total power consumption using their new process, with lower operational voltages. They have indicated this equates to a 30% speedup potential for existing chip applications. IBM has demonstrated the first SRAM chips manufactured using this process on CMOS, containing a 0.15 um2 cell size (picture on left). They have also completed a similar SOI implementation which will be suitable for mass production of future multi-core processors. This newest process technology research is the industry's answer to Intel's hafnium based high-k/metal gate technology, which is currently in use in all 45nm products at Intel. Intel has claimed a 10x reduction in gate leakage and other power and performance improvements with their solution, culminating to approximately the same reduction in overall power--about 30%. IBM's solution announced today will not be available until the 32nm process node. This will come in the second half of 2009, though it is likely any commercial products based on the technology will not be out until 2010. IBM's partner, AMD, had mentioned previously during the Technology Analyst day conference call that they were still examining the possbility of incorporating a high-k/metal gate solution at the 45nm process node. Read more ... IBM's press release.

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